The present invention relates to a system for recording and reproducing video and audio signals as digital signals, and more particularly, to a data detection method and apparatus thereof for use in a digital recording/reproducing system having a reference voltage adjustment unit for adjusting the reference voltage of a data detector in order to reproduce the recorded digital signal accurately.
A conventional digital recording/reproducing system records a signal onto a recording medium in the form of digital data. During a reproducing operation, an analog signal is picked up from the recording medium and is converted into the original digital data through the data detector.
FIG. 1 is a block diagram of a conventional data detection apparatus for use in a digital recording/reproducing system, for example, a non-return-to-zero inverted (NRZI) system.
Referring to FIG. 1, in recording data, the signal a to be recorded and the signal passed through a pre-coder 1 are summed in an adder 2 and are recorded onto the recording medium in the form of digital data by means of a recording head 5 via a recording equalizer 3 and a recording amplifier 4. At this time, pre-coder 1 performs a coding operation for preventing errors from being propagated.
When reproducing the signal recorded as described above, the data recorded onto the recording medium is read out as an analog signal by means of a pickup device such as a reproduction head 6. The read signal is amplified in a reproduction amplifier 7, and the analog signal is compensated through a reproduction equalizer 8. Adder 10 sums the output signal of reproduction equalizer 8 and the signal obtained by delaying the output signal of reproduction equalizer 8 by one clock cycle through delay 9 and then outputs the result to a data detector 20. In data detector 20, analog data is converted into digital data to then be output. The reproduction signal compensated in reproduction equalizer 8 is output to PLL 11. PLL 11 generates a clock signal whose phase is controlled and outputs the clock signal to the clock port of D flip-flop 25.
The conventional data detector 20 is constituted by a differential amplifier 21, first and second comparators 22 and 23, an OR gate 24 and a D flip-flop (F/F) 25.
Now, the operation of the thus-constituted data detector will be described.
First, the output signal e from adder 10 is input to differential amplifier 21. Then, the signal f having the same phase as the signal e is output via the non-inverting output port (+) of differential amplifier 21 and a signal g whose phase is inverted with respect to the input is output via the inverting output port (-). These signals f and g are input to the non-inverting input ports of first and second comparators 22 and 23, respectively, and a reference voltage V.sub.r is applied to the inverting input ports. Then, first comparator 22 compares the magnitude of the input signal f and the reference voltage V.sub.r. If the input signal f is larger than the reference voltage V.sub.r, a logic "high" is output, and if the input signal f is smaller than the reference voltage V.sub.r, a logic "low" is output. Similarly, second comparator 23 compares the magnitude of the input signal g and the reference voltage V.sub.r, to output a digital signal accordingly. OR gate 24 receives the outputs of the first and second comparators 22 and 23, performs an OR operation with respect thereto, and outputs a digital signal h to D flip-flop 25. D flip-flop 25 synchronizes the output of OR gate 24 with the clock of a clock counter constituted by a phase-locked loop (PLL) 11, to reproduce a digital signal i.
FIGS. 2A to 2M are operational waveforms of various parts for explaining the flow of signals shown in FIG. 1. FIG. 2A shows an input signal to be recorded, i.e., digital data corresponding to the signal a in FIG. 1. FIG. 2B shows a signal produced by summing the input signal a and the output of pre-coder 1, i.e., the signal b in FIG. 1.
FIG. 2C shows a signal produced by compensating the reproduced analog signal by means of reproduction equalizer 8, which corresponds to the signal c in FIG. 1. FIG. 2D shows the signal produced by delaying the output signal of reproduction equalizer 8 by means of delay 9, which corresponds to the signal d in FIG. 1. FIG. 2E shows a signal produced by summing the output signal of reproduction equalizer 8 and the output of delay 9, corresponding to the signal e in FIG. 1.
FIGS. 2F and 2G show input signals of each non-inverting input port of first and second comparators 22 and 23 shown in FIG. 1 and illustrate each magnitude of a first reference voltage V.sub.r1 and a second reference voltage V.sub.r2.
FIG. 2H shows an output signal h from OR gate 24 shown in FIG. 1, when the reference voltages of first and second comparators 22 and 23 are the first reference voltage V.sub.r1, where a clock signal is an output of PLL 11 shown in FIG. 1.
FIG. 2I shows a signal i reproduced from D flip-flop 25 shown in FIG. 1, when the reference voltages of first and second comparators 22 and 23 are the first reference voltage V.sub.r1.
FIG. 2J shows a pulse having an error margin of 25% with respect to jitter of the clock signal when the reference voltage is the first reference voltage V.sub.r1.
As shown in FIGS. 2H to 2J, the reproduced signal i has an error generated in a third bit. At this time, in view of the error margin, since the pulse widths of the second, third and fourth error margins are comparatively small, the probability of an error generation is high.
FIG. 2K shows the output of OR gate 24 when the reference voltages of first and second comparators 22 and 23 are V.sub.r2.
FIG. 2L shows a signal i reproduced from D flip-flop 25 shown in FIG. 1 when the reference voltages of first and second comparators 22 and 23 are first reference voltage V.sub.r2, where the oblique-lined fourth bit may be a logic "high" or a logic "low."
FIG. 2M shows a pulse having an error margin of 25% for jitter of the clock signal for the case of the reference voltage V.sub.r2, where a first error margin is nearly zero, as understood by its narrow pulse width, and the pulse widths of error margins are narrow on the average.
As described above, in a digital recording/reproduction system, the conventional data detection method has a considerably high probability of error generation. Also, the error generation is very sensitive to jitter of the reproduced signal and clock, due to time-axis variation.